

`define RAM1_DATA_WIDTH		96
`define RAM1_ADDR_WIDTH 	8
`timescale 1ns/1ps
module RAM1_96x256_DPRAM(
	ena,
	enb,
	clka, 
	addra, 
	dina, 
	douta, 
	clkb, 
	addrb, 
	dinb, 
	doutb,
	wea,
	web
);


input clka;
input ena;
input enb;
input [`RAM1_ADDR_WIDTH-1:0]addra; 
input [`RAM1_DATA_WIDTH-1:0]dina; 
output reg[`RAM1_DATA_WIDTH-1:0]douta; 
input clkb; 
input [`RAM1_ADDR_WIDTH-1:0]addrb; 
input [`RAM1_DATA_WIDTH-1:0]dinb; 
output reg[`RAM1_DATA_WIDTH-1:0]doutb;
input wea;
input web;

wire [95:0] douta_temp,doutb_temp;
SRAM_48x256_DPRAM SRAM_48x256_DPRAM_u0(
	.ena(ena),
	.enb(enb),
	.clka(clka), 
	.addra(addra), 
	.dina(dina[(`RAM1_DATA_WIDTH/2)-1:0]), 
	.douta(douta_temp[(`RAM1_DATA_WIDTH/2)-1:0]), 
	.clkb(clkb), 
	.addrb(addrb), 
	.dinb(dinb[(`RAM1_DATA_WIDTH/2)-1:0]), 
	.doutb(doutb_temp[(`RAM1_DATA_WIDTH/2)-1:0]),
	.wea(wea),
	.web(web)
);


SRAM_48x256_DPRAM SRAM_48x256_DPRAM_u1(
	.ena(ena),
	.enb(enb),
	.clka(clka), 
	.addra(addra), 
	.dina(dina[`RAM1_DATA_WIDTH-1:`RAM1_DATA_WIDTH/2]), 
	.douta(douta_temp[`RAM1_DATA_WIDTH-1:`RAM1_DATA_WIDTH/2]), 
	.clkb(clkb), 
	.addrb(addrb), 
	.dinb(dinb[`RAM1_DATA_WIDTH-1:`RAM1_DATA_WIDTH/2]), 
	.doutb(doutb_temp[`RAM1_DATA_WIDTH-1:`RAM1_DATA_WIDTH/2]),
	.wea(wea),
	.web(web)
);

always@(posedge clka)
begin
	douta <= douta_temp;
	doutb <= doutb_temp;
end 



endmodule

	




